Reseach RoadmapΒΆ
These are the main areas of research/development for the near future:
Currently DART optimizes FPGA resource usage and timing. In the future it will also optimize power;
The regulating bus/memory contention (aka the predictable bus manager) mechanisms are still not integrated into DART.;
Integrate the FRED framework with APP4MC/Amalthea to enable Model Based Engineering with FPGA offloading;
Integrate the FRED framework with Xilinx Vitis AI flow for accelerating deep learning applications;
Integrate the FRED framework with ROS2 for robotics and automonous vehicle applications;