Getting Started¶

This section summarizes the FRED Framework workflow and the steps required to run a FRED-based application on the FPGA. The proposed workflow can be divided into three phases: hw/sw partitioning, hardware design, software deployment.

The hw/sw partitioning phase is when the designer has to decide which parts of the target application will be offloaded to FPGA. Typically this is decided based on profiling data from the application, where the bottlenecks are usually good candidates for FPGA offloading. For each function to be offloaded there must have an equivalent hw IP, like those already provided in dart_ip repository. Finally, the applications timing requirements should also be extracted in this phase.

Next, is the hardware design phase, where DART produces the bitstreams and hardware partitions. Note that it is also possible to work with FRED Runtime with hardware designed with Xilinx DPR flow called Dynamic Function eXchange instead of DART. The difference is that it will require more time and experience with Xilinx tools to have an equivalent hardware design. Moreover, the timing analysis done by DART would not exist, and the designer would need to do it himself.

The software deployment phase needs a FRED-ready Linux distribution, like the one created with the Yocto layers meta-fred and meta-retis and Petalinux. Once the Linux image is ready, then starts the application software design. One can use a Yocto-based embedded software development flow, the recommended flow, or design the software directly on the board. The Linux image designed for FRED works with both approaches.

Here is the steps to build a Linux image for FRED:

$ wget https://raw.githubusercontent.com/fred-framework/fred-docs/main/docs/07_getting-started/build_img.sh .
$ chmod +x build_img.sh
$ wget https://raw.githubusercontent.com/fred-framework/meta-fred/main/scripts/pt-config
# wget bsp
$ ./build_img.sh -h

Or, it is possible to download from here a pre-built image for the ZCU-102 board with a basic example built-in.

Once the image is running on the board, To run the basic example, execute:

$ load_hw
$ fred-server &
$ sum-vec

The tutorials in DART repository are a good starting point for a development flow based on DART and FRED. The alternative is this other tutorial within Vivado Xilinx for the hardware design and FRED for the software deployment phase.